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FUJITSU SEMICONDUCTOR DATA SHEET
DS06-20206-5E
Semicustom
CMOS
Standard cell
CS81 Series
DESCRIPTION
The CS81 series 0.18 m CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CS81 can operate at a power-supply voltage of down to 1.1 V, substantially reducing power consumption.
FEATURES
* Technology * * * * * * * * * * * * * * * : 0.18 m silicon-gate CMOS, 3- to 6-layer wiring capable of integrating a mixture of highspeed processes and cells on a single chip (under development) Supply voltage : +1.8 V 0.15 V (normal) to +1.1 V 0.1 V Junction temperature range : -40 to +125 C Gate delay time : tpd = 11 ps (1.8 V, inverter, F/O = 1) Gate power consumption : Pd = 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1) Support for high speed (62.2 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps) interface macros for transmission Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (33 k typical) and bidirectional buffer cells Buffer cells dedicated to crystal oscillators Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others. including those under development) IP macros (CPU (FR, ARM7, ARM9), DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. including those under development) Capable of incorporating compiled cells (RAM/ROM/multiplier, and others.) Configurable internal bus circuits Advanced hardware/software co-design environment Short-term development using a timing driven layout tool Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued)
Copyright(c)1999-2007 FUJITSU LIMITED All rights reserved
CS81 Series
(Continued) * Hierarchical design environment for supporting large-scale circuits * Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture * Support for memory (RAM/ROM) SCAN * Support for memory (RAM) BIST * Support for boundary SCAN * Support for path delay test * A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA, LQFP)
MACRO LIBRARY (Including macros being prepared)
1.
* * * * * * * * * *
Logic cells (about 400 types)
Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR * * * * * * * * * * * Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND OR-AND Inverter OR Selector BUS Driver EOR Others
2. IP macros
CPU/DSP High speed interface macros Interface macro Multimedia processing macros Mixed signal macros Compiled macros PLL FR, SPARClite, ARM7, ARM9, Communications DSP, DSP for AV and others 622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps PCI, IEEE1394, USB, IrDA, and others JPEG, MPEG, and others ADC, DAC, OPAMP, and others RAM, ROM, multiplier, adder, multiplier-accumulator, and others Analog PLL, digital PLL
3. Special I/O interface macros
* T-LVTTL * LVDS * IEEE1394 * SSTL * PCI * SDRAM-I/F * HSTL * AGP * P-CML * USB
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CS81 Series
COMPILED CELLS
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS81 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.)
1. Clock synchronous single-port RAM (1 address : 1 RW)
* High density type/Partial write type Column type Memory capacity 4 16 * High speed type Column type 8 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
Memory capacity 256 to 144 K
Word range 64 to 2 K
Bit range 4 to 72
Unit bit
* Large scale partial write type Column type Memory capacity 16 24.5 K to 1179 K
Word range 4 K to 16 K
Bit range 6 to 72
Unit bit
2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)
* High density type/Partial write type Column type Memory capacity 4 16 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit bit bit
3. Clock synchronous register file (3 addresses : 1 W, 2 R)
Column type 1 Memory capacity 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
4. Clock synchronous register file (4 addresses : 2 W, 2 R)
Column type 1 Memory capacity 4608 Word range 4 to 64 Bit range 1 to 72 Unit bit
5. Clock synchronous ROM (1 addresses, 1 R)
Column type 16 Memory capacity 256 to 512 K Word range 128 to 4 K Bit range 2 to 128 Unit bit
6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R)
Column type 8 16 32 Memory capacity 256 to 32 K 384 to 32 K 512 to 32 K Word range 32 to 1 K 64 to 2 K 128 to 4 K Bit range 8 to 32 6 to 16 4 to 8 Unit bit bit bit 3
CS81 Series
ABSOLUTE MAXIMUM RATINGS
Rating Min -0.5 -0.5 -0.5 -55 -40 Max +2.5*2 +4.0*3 VDD+0.5 ( 2.5 V) *2 VDD+0.5 ( 4.0 V) *3 VDD+0.5 ( 2.5 V) *2 VDD+0.5 ( 4.0 V) *3 +125 +125 4 Clock input* : 200 Normal input : 100 100 3000/RO *7
5
Parameter Supply voltage*1 Input voltage*1 Output voltage*1 Storage temperature Junction temperature Output current*4 Input signal transmitting rate Output signal transmitting rate Output load capacitance Supply pin current *1 : VSS = 0 V
Symbol VDD VI VO Tst Tj IO RI RO CO ID
Unit V V V C C mA Mbps*6 Mbps*6 pF mA
*2 : Internal gate part in case of single power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *4 : DC current which continues more than 10 ms, or average DC current *5 : in case of I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one VDD/GND pin Frame Source type VDDE, VDDI, VDD, VSS YS, YI B VDDE VDDI, VDD, VSS VDDE, VDDI, VDD, VSS Maximum current [mA] Standard source Additional source 68 39 68 43 68 39 68 30 Number of layer 4, 5 3
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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CS81 Series
RECOMMENDED OPERATING CONDITIONS
* Single power supply (VDD = +1.8 V 0.15 V) Parameter Supply voltage (1.8 V supply voltage) "H" level input voltage (1.8 V CMOS) "L" level input voltage (1.8 V CMOS) Junction temperature Symbol VDD VIH VIL Tj Value Min 1.65 VDD x 0.65 -0.3 -40 Typ 1.8 Max 1.95 VDD + 0.3 VDD x 0.35 +125 (VSS = 0 V) Unit V V V C
* Dual power supply (VDDE = +3.3 V 0.3 V, VDDI = +1.8 V 0.15 V) Parameter Supply voltage "H" level input voltage "L" level input voltage Junction temperature 1.8 V supply voltage 3.3 V supply voltage 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Symbol VDDI VDDE VIH VIL Tj Value Min 1.65 3.0 VDDI x 0.65 2.0 -0.3 -0.3 -40 Typ 1.8 3.3 Max 1.95 3.6 VDDI + 0.3 VDDE + 0.3 VDDI x 0.35 +0.8 +125
(VSS = 0 V) Unit V V V C
* Dual power supply (VDDE = +3.3 V 0.3 V, VDDI = +1.5 V 0.1 V / +1.1 V 0.1 V) Parameter Symbol VDDE Supply voltage "H" level input voltage "L" level input voltage Junction temperature 3.3 V CMOS 3.3 V CMOS VDDI VIH VIL Tj Value Min 3.0 1.0 1.4 2.0 -0.3 -40 Typ 3.3 1.1 1.5 Max 3.6 1.2 1.6 VDDE + 0.3 +0.8 +125
(VSS = 0 V) Unit V V V V V C
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CS81 Series
* Dual power supply (VDDE = +2.5 V 0.2 V, VDDI = +1.8 V 0.15 V) Parameter Supply voltage "H" level input voltage "L" level input voltage Junction temperature 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Symbol VDDE VDDI VIH VIL Tj Value Min 2.3 1.65 VDDI x 0.65 1.7 -0.3 -0.3 -40 Typ 2.5 1.8 Max 2.7 1.95 VDDI + 0.3 VDDE + 0.3 VDDI x 0.35 +0.7 +125 (VSS = 0 V) Unit V V V V V V C
* Dual power supply (VDDE = +2.5 V 0.2 V, VDDI = +1.5 V 0.1 V / +1.1 V 0.1 V) Parameter Symbol VDDE Supply voltage "H" level input voltage "L" level input voltage Junction temperature 2.5 V CMOS 2.5 V CMOS VDDI VIH VIL Tj Value Min 2.3 1.0 1.4 1.7 -0.3 -40 Typ 2.5 1.1 1.5 Max 2.7 1.2 1.6 VDDE + 0.3 +0.7 +125
(VSS = 0 V) Unit V V V V V C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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CS81 Series
ELECTRICAL CHARACTERISTICS
1. DC characteristics
* Signal power supply : VDD = 1.8 V Parameter Supply Current "H" level output voltage "L" level output voltage Input leakage current Pull up/Pull down resistance Symbol IDDS VOH VOL IL RP IOL = +100 A Pull up VIL = 0 Pull down VIH = VDD Conditions IOH = -100 A (VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min VDD - 0.2 0 Typ 18 Max * VDD 0.2 5 Unit mA V V A k
* : For details of YS, YI, B frame of CS81 series, contact Fujitsu. * Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V (VDDE = 3.3 V 0.3 V, VDDI = 1.8 V 0.15 V / 1.5 V 0.1 V / 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Supply Current "H" level output voltage "L" level output voltage Symbol IDDS VOH4 VOH2 VOL4 VOL2 Conditions 3.3 V Output IOH = -100 A 1.8 V Output IOH = -100 A 3.3 V Output IOL = 100 A 1.8 V Output IOL = 100 A 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDI = 1.8 V0.15 V 3.3 V VDDE = 3.3 V0.3 V 1.8 V VDDI = 1.8 V0.15 V 1.8 V Pull up VIL=0 Pull down VIH=VDDI 3.3 V Pull up VIL=0 Pull down VIH=VDDE Value Min VDDE - 0.2 VDDI - 0.2 0 0 Typ *2 *2 18 5 k 10 33 80 Max *1 VDDE VDDI 0.2 0.2 Unit mA V V V V A
"H" level output V-I characteristics
"L" level output V-I characteristics Input leakage current
IL
Pull up/Pull down resistance
RP
*1 : For details of YS, YI, B frame of CS81 series, contact Fujitsu. *2 : Refer to the Fig.1 to 2.
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CS81 Series
* Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V (VDDE = 2.5 V 0.2 V, VDDI = 1.8 V 0.15 V / 1.5 V 0.1 V / 1.1 V 0.1 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Supply Current "H" level output voltage "L" level output voltage Input leakage current Symbol IDDS VOH3 VOH2 VOL3 VOL2 IL Conditions 2.5 V Output IOH = -100 A 1.8 V Output IOH = -100 A 2.5 V Output IOL = 100 A 1.8 V Output IOL = 100 A 2.5 V Pull up VIL=0 Pull down VIH=VDDE 1.8 V Pull up VIL=0 Pull down VIH=VDDI Value Min VDDE - 0.2 VDDI - 0.2 0 0 Typ 25 Max * VDDE VDDI 0.2 0.2 5 k 18 Unit mA V V V V A
Pull up/Pull down resistance
RP
* : For details of YS, YI, B frame of CS81 series, contact Fujitsu.
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CS81 Series
* V-I Characteristics Conditions (Fig 1, 2) Min : Process = Slow, Tj = +125 C, VDD = 3.6 V Typ : Process = TYPICAL, Tj = +25 C, VDD = 3.3 V Max : Process = FAST, Tj = -40 C, VDD = 3.0 V
VOH-VDD (V) -4.0 -3.0 -2.0 -1.0 0.0 0 -20 -40 -60 -80 Max -100 -120 IOH (mA) IOL (mA) 120 Max Min 100 80 60 40 Min 20 0 0.0 1.0 2.0 VOL (V) 3.0 4.0
Typ
Typ
Fig.1 V-I characteristics (3.3 V normal I/O L, M type)
VOH-VDD (V) -4.0 -3.0 -2.0 -1.0 0.0 0 -20 Min -40 IOH (mA) IOL (mA) -60 -80 -100 -120 -140 Max -160 160 140 120 100 80 60 Min 40 20 0 0.0 2.0 VOL (V) 3.0 4.0 Typ Max
Typ
1.0
Fig.2 V-I characteristics (3.3 V normal I/O H, V type)
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CS81 Series
2. AC characteristics
Parameter Delay time Symbol tpd*1
(VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Rating Min typ*2 x tmin*3 Typ typ*2 x ttyp*3 Max* typ*2 x tmax*3 Unit ns
*1 : Delay time = propagation delay time, enable time, disable time *2 : "typ" is calculated based on the cell specifications. *3 : Measurement conditions. Measurement condition VDD = 1.8 V0.15 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.5 V0.10 V, VSS = 0 V, Tj = -40 C to +125 C VDD = 1.1 V0.10 V, VSS = 0 V, Tj = -40 C to +125 C tmin 0.64 0.83 1.37 ttyp 1.00 1.31 2.45 tmax 1.58 2.05 4.88
Note : tpd max is calculated according to the maximum junction temperature (Tj) .
INPUT/OUTPUT PIN CAPACITANCE
(Tj = +25 C, VDD = VI = 0 V, f = 1 MHz) Parameter Input pin Output pin I/O pin Symbol CIN COUT CI/O Requirements Max 16 Max 16 Max 16 Unit pF pF pF
Note : Capacitance varies according to the package and the location of the pin.
DESIGN METHOD
SCCAD2 is the standard cell integrated design environment providing three major functions, enabling highquality, large-scale system LSIs to be developed in a shorter period of time. They include: the timing driven layout function for automatic placement/routing based on timing constraints to prevent timing problems after layout, the function for shortening the development cycle time by dividing a large-scale circuit and performing simultaneous logical/physical design of multiple circuits, and the function for automatically generating power/ signal wiring patterns while evaluating the supply voltage drop, signal noise, delay penalty, and crosstalk (Contact your nearest Fujitsu office for more information and availability).
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CS81 Series
PACKAGES
The table below lists the package types available. Consult Fujitsu for the combination of each package and the time of availability. Package Pin count 304 352 480 560 660 720 576 660 672 208 240 256 304 100 120 144 176 208 288 1089 1225 1369 1681 1849 2116 Material Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic Plastic
TAB-BGA
EBGA
HQFP
TQFP
LQFP FBGA
FCBGA
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CS81 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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